• 2 stop channels referring to one start channel
• Each of typ. 50 ps resolution, 65 ps BIN size
• 15 ns pulse pair resolution
• 4-fold multihit capability for each stop channel
• Measurement range 3.5 ns to 1,8 µs
• Selectable rising/falling edge sensitivity for each channel
• Enable pins for powerful windowing functionality
• The possibility to arbitrarily measure all events against each other

Digital TDCs use internal propagation delays of signals through gates to measure time intervals with very high precision. The diagram on the right clarifies the principal structure of such an absolute-time TDC. Intelligent circuit structures, redundant circuitry and special methods of layout on the chip make it possible to reconstruct the exact number of gates passed by the signal. The maximum possible resolution strongly depends on the maximum possible gate propagation delay on the chip.

 

The measuring unit is actuated by a START signal and stopped by a STOP signal. Based on the position of the ring oscillator and the coarse counter the time interval between START and STOP is calculated with a 20 Bit measurement range.

 

The BIN size (LSB) is typically 65 ps at 3.6 V and 25 °C ambient temperature. The gate propagation delay times strongly depend on temperature and voltage. Usually this is solved doing a calibration. During such a calibration the TDC measures 1 and 2 periods of the reference clock.
The measurement range is limited by size of the counter:
tyy = BIN x 26224 ~ 1.8 µs

	Time (Condition)	Description
tph	2.5 ns	Minimum pulse width
tpl	2.5 ns	Minimum pulse width
tss	3.5 ns min. 1.8 µs max.	Start to Stop
trr	15 ns	Rising edge to rising edge
tff	15 ns	Falling edge to falling edge
tva	560 ns uncalibrated 4.6 µs calibrated	Last hit to data valid
txx	No limits	Time interval between the stop channels
tyy	1.8 µs	Measurement range